In recent times, although demand for high-capacity dynamic random access memory (DRAM) is rapidly increasing, there is difficulty in increasing chip size, resulting in a limitation in increasing storage capacity of DRAM. The larger the chip size, the less the number of chips on each wafer, resulting in a reduction of productivity. Therefore, in recent times, intensive research is being conducted into a variety of methods for reducing a cell region by varying a cell layout so as to form a large number of memory cells on one wafer.
A buried gate structure has been developed as an example of the above-mentioned methods. The buried gate structure has some disadvantages. First, a leakage current caused by Gate Induced Drain Leakage (GIDL) characteristics increases between a conductive material (e.g., a gate electrode) and an N-type junction of an active region or between the conductive material and a storage node contact. Second, refresh characteristics (tREF, Refresh Time) of the whole semiconductor device deteriorate due to deterioration of GIDL characteristics.
To prevent a leakage current caused by GIDL characteristics from being increased, a conductive material (e.g., a gate electrode) of a buried gate is greatly etched so that an overlap region between a storage node contact and the conductive material can be minimized.
Assuming that a conductive material (gate electrode) of the buried gate is sufficiently etched, a leakage current caused by GIDL characteristics can be prevented from increasing. However, since buried gate resistance increases, the speed of a semiconductor device is increased, and current driving capability is deteriorated, resulting in the occurrence of Write-Recovery Time (twr) deterioration.